Comprehensive Analysis and Exploration of Design Space for Hardware Implementation of Advanced Encryption Standard (AES) Algorithm on FPGA Platform

Abstract

This research delves into the analysis and exploration of various design implementations of the AES encryption algorithm using Vivado software. Twenty-eight executions encompassing different implementation designs, employing resource sharing techniques and pipelining, are presented. Through synthesis and implementation, metrics such as static and dynamic power consumption, maximum circuit operating frequency, resource utilization, the number of slices per module, operational circuit efficiency, etc., are reported. To evaluate the results, four merit coefficients are considered, namely the ratio of operational efficiency to the number of consumed slices and dynamic power consumption, and the ratio of the maximum circuit operating frequency to the number of slices and dynamic power consumption. The highest operational efficiency and top two merit coefficients are obtained for various scenarios using pipelining and not utilizing resource sharing techniques. The highest third and fourth merit coefficients, along with the highest operating frequency, are achieved when employing both pipelining and resource sharing simultaneously. The optimal design is one that, considering trade-offs between metrics, can achieve the best results in terms of dynamic power consumption, resource utilization, operating frequency, and operational efficiency.

Keywords: Encryption, Synthesis, Maximum Operating Frequency, Circuit Operational Efficiency, Merit Coefficient